发明名称 RISC microprocessor with integrated bus control unit - connects read=write buffer, for storing data, address and control signals, to bus interface and to second control unit, which controls external bus for coupling peripherals to microprocessor
摘要 The microprocessor includes a bus (1) connected to a central processor (10) and a second bus (5) connected to an integrated peripheral device (11). A read-write buffer memory (6) is connected to a bus interface (3) and to a control unit (7). The control unit controls an external bus (8) for connection to external peripheral devices (12). The read-write buffer memory stores data, address, and control signals. The control signals include information on data width. A signal is generated on the first (1) or second bus (5) when the read-write buffer memory is full. The control device allows block reading from the external bus (8) to the buffer memory. ADVANTAGE - Processor is not adversely affected by peripheral devices.
申请公布号 DE4336353(A1) 申请公布日期 1994.06.09
申请号 DE19934336353 申请日期 1993.10.25
申请人 SIEMENS AG, 80333 MUENCHEN 发明人 MARIUTTI, PETER, DIPL.-ING., 83730 FISCHBACHAU;SCHOENBERGER, FRANZ, DIPL.-ING., 80937 MUENCHEN;SULZER, HANS, DIPL.-ING., 85435 ERDING;SCHMID, RICHARD, DIPL.-ING., 81379 MUENCHEN;JOHN, WOLFGANG, DIPL.-ING., 80809 MUENCHEN;ROHM, PETER, DIPL.-ING., 85276 PFAFFENHOFEN
分类号 G06F13/40;(IPC1-7):G06F12/08 主分类号 G06F13/40
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