摘要 |
<p>The invention provides fast generation of flag signals for devices, such as first-in first-out buffers, by looking-ahead and predetermining flag signals for possible future states of the device. The look-ahead signal generator, in one embodiment of the invention, uses odd/even read counters (203, 204) and odd/even write counters (201, 202), controlled by clock signals (WEVEN, WODD, REVEN, RODD), which outputs thereof are coupled, respectively, to comparators (205, 206) for generating flag signals EQE and EQO which in turn are multiplexed through pass-gates (503, 512) to the FLAG output terminal of the look-ahead signal generator. Pass-gates (503, 512) are respectively controlled by inverters (502, 511) connected in series with NAND gates (501, 510). The other two series connections of NAND gates (504, 507) and inverters (505, 508) control the multiplexing of other possible future states of the device, to the FLAG output terminal of the look-ahead signal generator.</p> |