发明名称 |
Range count and main memory address accounting system |
摘要 |
In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus for asynchronous intercommunication, an array of counters responsive to both hardware and firmware are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control.
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申请公布号 |
US4204250(A) |
申请公布日期 |
1980.05.20 |
申请号 |
US19770821900 |
申请日期 |
1977.08.04 |
申请人 |
HONEYWELL INFORMATION SYSTEMS INC |
发明人 |
GETSON, EDWARD F JR;KELLEY, JOHN H;MCLAUGHLIN, ALBERT T;RATHBUN, DONALD J |
分类号 |
G06F5/10;G06F5/14;G06F13/12;G06F13/28;(IPC1-7):G06F13/00 |
主分类号 |
G06F5/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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