发明名称 Data storage arrangement.
摘要 <p>In a data processing system utilising fast-access cache memory, data words written in to the cache from main memory are immediately read and checked against the original, any discrepancies resulting in the lock-out of that cache location so that next time the processor calls up that data word it is again read from main memory and is written into another location in cache. The system is thereby tolerant of defective cache locations. <IMAGE></p>
申请公布号 EP0600729(A1) 申请公布日期 1994.06.08
申请号 EP19930309620 申请日期 1993.12.01
申请人 PLESSEY SEMICONDUCTORS LIMITED 发明人 PHILLIPS, IAN
分类号 G06F11/16;G06F12/08;G11C29/00;(IPC1-7):G06F11/00 主分类号 G06F11/16
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