Coherency for write-back cache in a system designed for write-through cache.

摘要

A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching, and maintain cache coherency, in a 486-type microprocessor when installed in a multi-master computer system that supports only write-through cache (i.e., the system does not support a write-back protocol for maintaining cache coherency). The write-back coherency system includes: (a) a dirty data ( BARB) "export-on-HOLD" function, (b) an instantaneous-invalidation (PDIRTY) function, (c) a latency-minimization (X%DIRTY) function, and (d) an invalidate cache (INVD) instruction-execution function. For (a) the export-on-HOLD function, in response to an arbitration-request, a data export operation writes back cache locations containing dirty data, and then arbitration-acknowledge is returned to the requesting bus master and the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away. While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master. For (b) the instantaneous invalidation function, logic indicates when the cache does not contain dirty data, such that the invalidation logic can perform invalidation operations without first performing export operations. For (c) the latency minimization function, logic dynamically switches the cache from write-back to write-through mode during any period in which a write would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.