| 摘要 |
<p>Method and circuit for locking on frame synchronisation in telecommunications systems, based on digital techniques, especially SDH telecommunications systems. It enables the programming of parameters which optimise the alignment strategy, while maintaining a simple circuit implementation. The proposed system employs aggregation of the bits of the sequence received in groups of bits which are compared with the corresponding bits of the synchronisation word, allowing predetermined error levels xr, xv, in the individual groups of bits. The system further provides for checking when predetermined thresholds Sr, Sv are exceeded in the number of groups of received bits. <IMAGE></p> |
