Semiconductor intergrated circuit having delay circuit with voltage-to-delay characteristics proportional to power voltage level.

摘要

A semiconductor memory device has an addressable data storage (12 to 16) powered with an internal step-down power voltage (Vint) for storing data bits, a signal buffer circuit (19i) powered with a non-step-down power voltage (Vext) for producing an internal output enable signal (IOE), an output data buffer circuit (17) powered with the non-step-down power voltage and enabled with the internal output enable signal for producing an output data signal from a read-out data bit and a delay circuit (19j) connected between the signal buffer circuit and the output data buffer circuit for introducing delay into propagation of the internal output enable signal, and the delay circuit is implemented by a plurality of complementary inverters connected in cascade, wherein the p-channel type field effect transistors of the complementary inverters have source nodes and channel respectively biased with the step-down power voltage and the non-step-down power voltage so that the delay is proportional to the external power voltage.