| 摘要 |
<p>PURPOSE:To eliminate adverse influence on the working speed of a semiconductor memory by connecting plural transistors in parallel as the loads of both bit and dummy bit lines and using the transistors of the same type to plural transistors for bit line loads and those for dummy bit line loads respectively. CONSTITUTION:The bit line load transistors LD and the dummy bit line load transistors DLD contain plural MOS transistors (P1, P2) and (P3-P7) which are connected in parallel respectively. These MOS transistors are used in the single same type or >=2 types. As a result, the overall load ratio is always constant despite the conversion difference of patterns caused by the minute elements together with the variance in channel length and channel width. Then the unbalance is not easily produced for working speeds between the '1' and '0' reading actions. Thus it is possible to eliminate the adverse influence on the working speed.</p> |
