Clock recovery circuit.

摘要

In a clock recovery circuit, an asynchronous oscillator generates a first clock pulse at a frequency n times the frequency of a baseband signal. A sampler samples the baseband signal in response to the first clock pulses. A flip-flop holds and delivers the sampled signal in response to a second clock pulse supplied from a voltage-controlled oscillator. The time difference between the first clock pulse and the second clock pulse is detected and a set of tap-gain values is selected according to the time difference. The sample delivered from the flip-flop is successively delayed by a tapped delay line to produce tap signals which are respectively weighted with the selected tap-gain values. The weighted samples are summed to estimate an intermediate sample. A clock phase error of the estimated sample with respect to the clock timing of the transmitted signal is determined for controlling the VCO. <IMAGE>