发明名称 FRAME TRANSFER CIRCUIT
摘要 PURPOSE:To realize a frame transfer circuit in which a stuff bit is positioned at the permitted position of a frame after a transfer processing, by a simple circuit whose data delay is the minimum. CONSTITUTION:This circuit is equipped with a shift register means 1 which inputs a received signal (1) and a first identification signal (2) indicating the validity and invalidity, writes the data at the time of the validity of the first identification signal, and stops the writing at the time of the invalidity. And also, the circuit is equipped with a select means 2 which selects the output of the shift regist means by an input address, and a control part 3 which inputs the first identification signal (2) and a second identification signal (4) indicating a valid part in a transmission signal (3), and transmits the address to the select means 2 so that the data without any omission or overlap can be taken out from the shift register means 1 at the time of the validity of the second identification signal, and so that the overlapped data can be taken out at the time of the invalidity. And also, the circuit is equipped with an identification signal generating part 4 which checks the number of the data of the shift regist means not yet taken-out, changes the length of the invalid part of the second identification signal when the number of the data not yet taken-out data is beyond a prescribed number, and generates the second identification signal for holding the number of the untaken-out data of the shift register means 1 to be the prescribed number.
申请公布号 JPH06152557(A) 申请公布日期 1994.05.31
申请号 JP19920295471 申请日期 1992.11.05
申请人 FUJITSU LTD 发明人 KUDOU SHIYOUJI
分类号 H04J3/00;H04J3/06;H04J3/07;H04L7/00;H04L7/08 主分类号 H04J3/00
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