| 摘要 |
PURPOSE:To obtain a characteristic close to synchronization detection by improv ing considerably an error rate and to secure high speed synchronization. CONSTITUTION:A 1-bit delay detection output and a 1-bit delay detection imaginary output are obtained from a delay detection circuit 110 based on a sample of a sampling circuit 1. A metric generation maximum likelihood path selection circuit 120 obtains the branch metrics as a scale of the likelihood of a phase difference state between sampling points of time based on two delay detection outputs through calculation and the branch metrics are added to obtain a path metric of a phase difference series and a register circuit 130 outputs decoded data. |
