| 摘要 |
<p>PURPOSE:To generate a multi-phase clock having different clock pulse width in each phase without changing the period of the multi-phase clock even when power supply voltage is changed. CONSTITUTION:This multi-phase clock generating circuit has cascake-connected FFs 1 to 4 for inputting a reference clock, dividing the frequency of the input signal and allowing to be reset by a reset signal, output signals 101, 302 from the FFs 1, 3 are inputted to an AND gate 10, its output signal is outputted as a clock phi1, a signal 701 obtained by delaying the output signal, 101 through a delay circuit 7 and an output signal 301 from the FF 3 are inputted to an AND gate 11, and the output signal of the gate 11 is outputted as a clock phi1. A signal 601 obtained by delaying an output 102 from the FFI through a delay circuit 5 and the output signal, 301 of the FF 3 are inputted to an AND gate 8 and an output signal from the gate 8 is outputted as a clock phi2. The output signal 102 of the FF 1 and the output signal 301 of the FF 3 are inputted to an AND gate 9 and an output signal from the gate 9 is outputted as a clock phi3 so as to obtain a multi-phase clock signal.</p> |
