发明名称 COLUMN SELECTING CIRCUIT
摘要 <p>PURPOSE:To decrease a peak current without decreasing operation speed by operating only a sense amplifier of a bit line connected to a data line at high speed and operating the other sense amplifiers at low speed, in a memory. CONSTITUTION:When bit lines BLO and /BLO are accessed, a sense amplifier 1 is operated at high speed making gates 4, 5, 18, 19 an ON state, and sense amplifiers 2, 3 are operated at low speed making gates 7, 9, 21, 23 of the other sense amplifiers an OFF state. Thereby, even if many sense amplifiers simultaneously operate accompanying increasing memory capacity, since a peak current can be decreased without slowing access time while access time can be shortened without increasing a peak current, it is useful for increasing memory capacity.</p>
申请公布号 JPH06150649(A) 申请公布日期 1994.05.31
申请号 JP19920299484 申请日期 1992.11.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUMOTO AKIHIRO;MORI TOSHIKI
分类号 G11C11/419;G11C11/401;G11C11/407;G11C11/409;G11C17/00;(IPC1-7):G11C11/407 主分类号 G11C11/419
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