发明名称 Method and apparatus for testing and configuring the width of portions of a memory
摘要 A circuit and a related process are utilized in a computer system for testing and configuring the width of various portions of memory in a memory array. The circuit captures a state of a memory width control signal (MEMCS16) during a test and configuration cycle, retains the state of the MEMCS16 signal for various blocks of memory, and controls the state of the MEMCS16 signal when a memory access to a particular memory block is made. The circuit tests the state of the MEMCS16 signal for various blocks of the system memory map and thereafter configures a memory control register appropriately. The state of the MEMCS16 signal is retained by a latch when a particular 128K region is accessed and a valid address is present on the address lines. The output of the latch is provided as a processor-readable test result in a bit of a control/test register.
申请公布号 US5317712(A) 申请公布日期 1994.05.31
申请号 US19910812072 申请日期 1991.12.19
申请人 INTEL CORPORATION 发明人 PEEK, GREG A.;CEDROS, CRAIG D.
分类号 G06F12/04;G06F12/06;G06F13/42;(IPC1-7):G06F12/00;G06F13/00 主分类号 G06F12/04
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