发明名称 |
Bit decoder for generating select and restore signals simultaneously |
摘要 |
A bit decoder for a memory array includes a decode NOR/OR circuit coupled to an output driver circuit. The decode NOR/OR circuit includes a plurality of input signals connected to respective input FET's all of which are connected in parallel between a common source and a common drain node. One input is also connected to an active pullup FET which is connected in series with the input FET's at the common drain node and which is always maintained slightly on. A bipolar transistor pulls down the common drain node and a bleeder FET pulls down the common source node. The output driver is a BICMOS circuit that provides both the bit selection and bit refresh signals which are of opposite phase.
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申请公布号 |
US5317541(A) |
申请公布日期 |
1994.05.31 |
申请号 |
US19910728021 |
申请日期 |
1991.07.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHAN, YUEN H. |
分类号 |
G11C11/413;G11C8/10;G11C8/12;G11C11/418;(IPC1-7):G11C7/00;G11C8/00;H03K19/02 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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