Block parity processor for asynchronous communication network - uses parity memory in parallel with data word memory to allow quasi-simultaneous computation of parity for retransmission

摘要

The processor is part of communication equipment that receives then retransmits data, computing new block parity data that is sent at the head of the message. The units of message transfer (octets) are stored in a memory (10) as they are received. They are subsequently successively removed from this memory by a data sending circuit (15). Incoming data is also supplied to a parity computation circuit (13) which receives the same data as the memory. The parity computer delivers bits to a parity memory (14) which has its output connected to the sender circuit. Reading and writing of the parity memory is controlled (11,12) in parallel with the first memory. ADVANTAGE - Reduces buffer size needed for block parity computation.