| 摘要 |
An interstage amplifier for a pipelined analog-to-digital converter comprises an operational amplifier (50) having two balanced amplifying paths; a first pair of capacitors (55, 58); a second pair of capacitors (56, 57); and switching means (59-62) connected to the capacitors and said amplifier and arranged for: (i) during a first phase, enabling the first pair of capacitors (55, 58) to receive a respective first sample of a first signal; (ii) during a second phase, enabling the second pair of capacitors (56, 57) to receive a second sample of the first signal; (iii) during a third phase, enabling the first pair of capacitors (55, 58) to receive a first sample of a second or reference signal and to enable charge to be transferred from each of the first pair of capacitors by way of a respective path of the amplifier to a respective one of the second pair of capacitors; and (iv) during a fourth phase, enabling the second pair of capacitors (56, 57) to receive a second sample of the said second or reference signal and to enable charge to be transferred from each of the second pair of capacitors by way of a respective path of the amplifier to the respective one of the first pair of capacitors. The arrangement provides first-order correction of capacitor mismatch. The switching means (59-62) interchanges the input connections and interchanges the output connections of the amplifying paths to compensate for offset in the amplifier (50). The amplifier and additional switches may be arranged to constitute two successive interstage amplifiers. |
