| 摘要 |
forming a gate electrode, source and drain region on a predetermined portion of a substrate; forming a sidewall insulating layer on the side of the gate electrode, and forming a bit line between the gate electrode to come into contact with the drain region; sequentially forming a nitride and PSG layer on the overall surface of the substrate, selectively removing a portion of the PSG layer excepting a portion in which storage node will be formed, and then depositing a BPSG to planarize the surface of the substrate; etching back the BPSG layer to expose the PSG layer, and removing the exposed PSG layer and nitride to open the source region; depositing a storage node polysilicon and insulating layer; etching back the insulating layer to expose the storage node polysilicon, selectively etching the exposed storage node polysilicon, and then removing the remaining insulating layer to form storage node; and forming a dielectric layer and plate electrode on the surface of the storage node, thereby obtaining self-aligned node contact, and improving reliability of the device.
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