发明名称 Peak hold circuit with improved linearity
摘要 A peak hold circuit includes an operational amplifier in a continually closed feedback loop and a peak hold capacitor with a discharge path. An input signal is received at a first input of the amplifier, and the output of the amplifier is fed to a first transistor then fed back therefrom to a second input of the amplifier. A current sink is coupled to the first transistor for drawing a current therefrom so that the feedback signal is continually provided to the second amplifier input, ensuring that the amplifier is in a continually closed feedback loop. The output of the amplifier is supplied to the peak hold capacitor through a second transistor.
申请公布号 US5315168(A) 申请公布日期 1994.05.24
申请号 US19930054035 申请日期 1993.04.28
申请人 FUJITSU LIMITED 发明人 NORTON, JR., DAVID E.
分类号 G01R19/04;H03K5/1532;(IPC1-7):H03K5/24 主分类号 G01R19/04
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