发明名称 |
Binary data generating circuit and A/D converter having immunity to noise |
摘要 |
An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.
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申请公布号 |
US5315301(A) |
申请公布日期 |
1994.05.24 |
申请号 |
US19920976056 |
申请日期 |
1992.11.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
HOSOTANI, SHIRO;MIKI, TAKAHIRO;ITO, MASAO |
分类号 |
H03M1/08;H03M1/06;H03M1/36;(IPC1-7):H03M1/06 |
主分类号 |
H03M1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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