| 摘要 |
The output buffer includes first and second N channel FETs serially connected between a ground terminal and a voltage supply terminal and having a common terminal connected to an output terminal. Third and fourth N channel FETs are serially connected between the ground terminal and the voltage supply terminal and have a common terminal connected to the output terminal. A first logic circuit responds to data input (DIN) signals and an operation enable bar (OEB) signal for applying a conductive bias voltage to the third N channel FET, and a second logic circuit responds to the DIN signals and the OEB signal for applying a conductive bias voltage to the fourth N channel FET. A first P channel FET couples the conductive bias voltage on the third N channel FET to the first N channel FET, and a second P channel FET couples the conductive bias on the fourth N channel FET to the second N channel FET. The P channel transistors are mask programmable weak conductors thus limiting the rate of conductive bias applied to the first N channel FET and to the second N channel FET. Fifth and sixth N channel FETs are connected between the gate terminals of the first and second FETs and circuit ground for preventing conduction of the first and second FETs when the fifth and sixth FETs are conductive.
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