| 摘要 |
A circuit for detecting a code violation in an alternate mark inversion signal comprises a first detecting circuit receiving the alternate mark inversion signal for generating a first detection signal at continuous occurrence of two first polarity signals without interleaving a second polarity signal, the first and second polarity signals being indicative of the same binary logical level, and a second detecting circuit receiving the alternate mark inversion signal for generating a second detection signal at continuous occurrence of two second polarity signals without interleaving the first polarity signal. The first detection signal is inputted to a first enable signal generating circuit for generating a first enable signal having a predetermined active period, and the second detection signal is inputted to a second enable signal generating circuit for generating a second enable signal having a predetermined active period. A first violation detection circuit receives the second detection signal and the first enable signal and generates a first code violation detection signal when the second detection signal is generated during the active period of the first enable signal. A second violation detection circuit receives the first detection signal and the second enable signal and generates a second code violation detection signal when the first detection signal is generated during the active period of the second enable signal.
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