发明名称 |
Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion |
摘要 |
A data output buffer includes a data driving circuit having a pull-up transistor responsive to a first signal and a pull-down transistor responsive to a second signal, a first control circuit for regulating the slope of the first signal to be less steep after reaching the threshold of the pull-up transistor than before reaching the threshold of the pull-up transistor, and a second control circuit for regulating the slope of the second signal to be less steep after reaching the threshold of the pull-down transistor than before reaching the threshold of the pull-down transistor. As a result, noise generated by the transition of the output signal of the data output buffer is reduced without affecting operation speed.
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申请公布号 |
US5315173(A) |
申请公布日期 |
1994.05.24 |
申请号 |
US19920898535 |
申请日期 |
1992.06.15 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, SEUNG-KEUN;KWAK, CHOONG-KEUN;KIM, CHANG-RAE |
分类号 |
G11C11/417;G11C7/02;G11C11/409;H01L27/10;H03K17/16;H03K19/003;H03K19/0175;(IPC1-7):H03K5/12;H03K19/094 |
主分类号 |
G11C11/417 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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