Memory circuit test system using separate ROM having test values stored therein

摘要

A memory test method and system are described which comprises a first memory array and a second memory array coupled to a plurality of row address lines within a memory system. During the testing of the memory system, row decode logic is used to sequentially access each of the row address lines The second memory array stores a predetermined value associated with each of the row address lines. Accordingly, accuracy of the row decode logic and continuity of the row address lines can be verified without the necessity of programming each memory location within the first memory array.