| 摘要 |
<p>PURPOSE:To prevent abnormal data read out by a temporary overtaking of a readout address by a write address or data written in an asynchronous state from being attached on a part before normal effective data. CONSTITUTION:A fast timing generating part 3 generates a write reset pulse at the forefront of a first time slot after the establishment of frame synchronization and a time slot designation signal at every frame based on a frame pulse and a synchronous state signal, and a slow timing generating part 4 generates a read reset pulse based on the write reset pulse, and they are supplied to elastic store 2. An abnormal data control part 5 generates an output control signal which suppresses the output of the readout data in the elastic store until the leading data of a specific time slot after the establishment of the frame synchronization is outputted, and supplies it to the elastic store.</p> |
