| 摘要 |
forming a gate oxide 2, polysilicon layer 6 and nitride 5 on a silicon substrate 1 sequentiallly; patternin the nitride layer so as to be left only on gate region, and implanting n-type ion into the substrate using the nitride pattern; forming a spacer 4 on the side wall of the nitride pattern 5, and etching the polysiicon layer using the nitride pattern and spacer as mask; oxidizing the both side portion of the polysilicon layer; removing the nitride layer, and performing channel ion implantation using the spacer as mask; etching the gate oxde using the nitride layer as mask; and forming the single crystalline silicon layer and polysilicon layer on the source and drain region and gate region respectively through selective epitaxy, and forming a highly doped n-type region by implantation of As ion into the single crystalline silicon layer, thereby to prevent doping compensation effect and reduce the short channel effect.
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