| 摘要 |
- Such a numerical shift register including a succession of several master/slave flip-flops (M/S) controlled by a clock signal (H), comprises at least between two master/slave flip-flops (M/S) a switching device (C) which makes it possible to choose between a serial loading mode and a parallel loading mode of the flip-flop which it precedes. - The switching device (C) includes a differential stage used in serial mode (Cs) composed of a pair of transistors (T1, T2), and a differential stage used in parallel mode (Cp) composed of at least two differential pairs of transistors (T3, T4 and T3', T4') mounted in parallel, some only of the transistors of the output branch (T4') being connected to the input of the flip-flop which follows the switching device so as to avoid the saturation of the input transistor (Te) of this flip-flop (M/S) in parallel loading mode. Application to the numerical processing of the video signal downstream of analog/digital converters for example. <IMAGE> |
