| 摘要 |
<p>A method for forming an integrated circuit with a planarized dielectric (e.g., 43) is disclosed. Runners (e.g., 25) and gates (e.g., 23) are covered with a protective dielectric layer (e.g., 21). Then a conventional dielectric (e.g., 43) is deposited and planarized over the entire circuit surface. When windows (e.g., 49, 47) are opened to runners and to source (e.g.,27)/drain (e.g., 29) regions, the protective dielectric (e.g., 21) helps to slow the etch process over the runner (e.g., 25), thus protecting the runner (e.g., 25) from damage during the extra time required for the etch process to reach the source (e.g., 27) or drain (e.g., 29).</p> |
