发明名称 Sample and hold circuit with full signal modulation compensation using bipolar transistors of single conductivity type
摘要 A diode bridge (12) includes a plurality of diodes (D1,D2,D3,D4) for coupling an input voltage signal (Vin) through a resistor (RH) to a holding capacitor (CH) for sampling when the diodes (D1,D2,D3,D4) are forward biased, and uncoupling the voltage signal (Vin) from the capacitor (CH) for holding when the diodes (D1,D2,D3,D4) are reverse biased. A constant current drain (S1) causes a constant bias current (IBIAS) to flow out of the bridge (12) through first and second bias current nodes (N1,N2) to a voltage source (VEE). The nodes (N1,N2) are also connected through current source resistors (R1,R2) to a voltage source (VCC). A first current regulator (72) is bootstrapped to the input signal (Vin) and regulates first and second bias currents flowing into the nodes (N1,N2) to constant values (IBIAS/2) to compensate for resistive current source modulation. A second current regulator (92) is also bootstrapped to the input signal (Vin) and regulates bias current flowing through the resistor (RH) into the junction (20) between the resistor (RH) and the capacitor (CH) to a constant value (IBIAS/4) to compensate for output slew current modulation.
申请公布号 US5313113(A) 申请公布日期 1994.05.17
申请号 US19920870369 申请日期 1992.04.17
申请人 HUGHES AIRCRAFT COMPANY 发明人 LINDER, LLOYD F.
分类号 G01R13/34;G11C27/02;(IPC1-7):H03K5/24 主分类号 G01R13/34
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