发明名称 |
Bit aligned data block transfer method and apparatus |
摘要 |
The number of required clock periods in a bit aligned block transfer operation may be reduced by analyzing the logical relationship between source, destination and pattern operands prior to fetching these operands from memory. If the result of the raster operation can be determined without actually using the value of any of the operands, the result is provided without reading memory values. When the raster operation will have no effect on the existing destination operand, the write operation is also canceled.
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申请公布号 |
US5313576(A) |
申请公布日期 |
1994.05.17 |
申请号 |
US19900617198 |
申请日期 |
1990.11.23 |
申请人 |
NETWORK COMPUTING DEVICES, INC. |
发明人 |
PROVIDENZA, JOHN R.;BOEKELHEIDE, LEE |
分类号 |
G06F7/00;G09G5/393;(IPC1-7):G06F15/62 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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