发明名称 |
Apparatus and method for preventing I/O bandwidth limitations in fast fourier transform processors |
摘要 |
A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.
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申请公布号 |
US5313413(A) |
申请公布日期 |
1994.05.17 |
申请号 |
US19930027934 |
申请日期 |
1993.03.08 |
申请人 |
SHARP MICROELECTRONICS TECHNOLOGY INC.;SHARP KABUSHIKI KAISHA |
发明人 |
BHATIA, ROHIT;FURUTA, MASARU |
分类号 |
G02B6/12;G02B6/122;G02B6/132;G02F1/01;G02F1/065;G02F1/35;G02F1/355;G02F1/361;G06F9/38;G06F17/14;(IPC1-7):G06F15/00 |
主分类号 |
G02B6/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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