| 摘要 |
A series-to-parallel converter (26) converts an input code sequence to first to N-th code sequences with input clocks frequency divided by N into circuit clocks, based on which a frame pulse is generated. Among concurrency detectors (41) which are supplied with the frame pulse in common and with detection signals produced when first to N-th synchronization patterns are detected in the respective code sequences and are for producing nonconcurrent results when the detection signals are nonconcurrent with the frame pulse, a particular detector produces an earliest concurrent result to disable other detectors when the frame pulse is concurrent with one of the detection signals that is supplied thereto. These other detectors are enabled when the particular detector produces a nonconcurrent result due to collapse of frame synchronism. Through an AND gate (43), the nonconcurrent results inhibit the circuit clocks.
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