| 摘要 |
A digitally controlled asymmetrical delay circuit (DCADC) is described in which the amount of delay for an input transitioning in one direction (e.g. low to high) is controlled independently from the amount of delay for the input signal transitioning in the opposite direction (high to low). This digitally controlled asymmetrical delay circuit is applied to a memory address decode circuit. The DCADC is controlled by the WRITE/READ signal such that there is minimal delay when the WRITE signal is low (the READ signal is high), minimizing the delay introduced in the access time. When the WRITE signal is high (the READ signal is low), extra delay is added to the selection relative to the deselection of a memory location. In this manner, input noise during a WRITE is filtered out without slowing the access time.
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