| 摘要 |
An apparatus and method of constructing a sinusoidal output signal corresponding to a predetermined harmonic component of a sinusoidal input signal is described. The input signal is multiplied by a specified harmonic component of cosine and sine reference signals to divide it into direct and quadrature signals. The direct and quadrature signals are proportional to the amplitude of the specified harmonic component of the reference signals at the specified phase. Each cycle of the direct and quadrature signals is sampled a number of times to form direct and quadrature signal segments. The direct and quadrature signal segments are respectively placed in direct and quadrature circular buffers. Each circular buffer includes a number of formerly sampled segments. Before adding a new segment, the oldest segment in the buffer is dropped. Direct and quadrature amplitude sums, corresponding to the sum of all sampled segments within the respective circular buffers, are maintained. The buffers act as an averaging or integrating filter for the segment amplitude values. The instantaneous direct and quadrature amplitude sums are respectively re-multiplied by the same specified harmonic component of the cosine and sine reference signals to produce in-phase direct and quadrature fundamental signal components. These signals are then added to form a vector sum constituting a one-cycle delayed output signal which corresponds, in phase and amplitude, to the specified harmonic component of the input signal. |
