| 摘要 |
<p>PURPOSE:To keep the original clock signal from the outside of an information processing part to low frequency, raising the machine cycle of an information processing system, by synchronizing the low frequency source clock signal from the outside of an information processing part and the high frequency clock signal of the inside of the information processing part. CONSTITUTION:An information processing part 1002 is composed of a clock generator 101, a polyphase clock signal 111, a logical device 102 and an interface circuit 103, etc. The clock generator 101 receives an original clock signal 1011 from the outside and outputs two-layer clock signals K1, K2. The duty of an original clock signal K is not necessary to be 50% and the K1, K2 are synchronized with the K. The generated polyphase clock signal 111 is transmitted to the logical device 102 and the interface circuit 103, and the logical device 102 is controlled by the clock signals K1, K2. In order to shorten the machine cycle, the deviation of the duty of the clock signals and clock screw are required to be extremely smaller.</p> |
