发明名称 DIGITAL DATA RECEIVING CIRCUIT
摘要 <p>PURPOSE:To shorten the time required for reproduction of a data decoding clock and to omit the long bit synchronizing preamble by using a prescribed clock phase as the initial value of each slot of the clock phase used for reproduction of the clock. CONSTITUTION:A clock reproducing part 1 which reproduces a decoding clock out of a received signal includes a phase detecting part 4 which detects the clock phase out of the received signal, a clock generating part 5 which generates a decoding clock based on the phase information, and a phase storage part 6. Then a decoding part 2 decodes the received signal by the decoding clock received from the part 1, and a data recognizing part 3 detects the error rate of the decoded data and the slot timing to input them to the part 1. Thus the part 1 stores the phase information on the clock based on the information on the data error rate and the slot timing and also controls the reading of the clock phase information.</p>
申请公布号 JPH06132923(A) 申请公布日期 1994.05.13
申请号 JP19920279730 申请日期 1992.10.19
申请人 NEC CORP 发明人 SHIGEMOTO NAOHITO
分类号 H04J3/06;H04L7/00;H04L7/04;H04L7/10;H04L25/40;(IPC1-7):H04J3/06 主分类号 H04J3/06
代理机构 代理人
主权项
地址