发明名称 |
CPU with integrated multiply/accumulate unit |
摘要 |
An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.
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申请公布号 |
US5311458(A) |
申请公布日期 |
1994.05.10 |
申请号 |
US19920975399 |
申请日期 |
1992.11.10 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
HAINES, RALPH W.;PHILLIPS, GARY D.;COVEY, D. KEVIN;THOMSON, THOMAS W. S. |
分类号 |
G06F7/533;G06F7/52;G06F7/53;G06F7/544;G06F9/38;G06F12/08;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/533 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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