| 摘要 |
PCT No. PCT/JP91/01584 Sec. 371 Date Apr. 12, 1993 Sec. 102(e) Date Apr. 12, 1993 PCT Filed Nov. 19, 1991 PCT Pub. No. WO92/09083 PCT Pub. Date May 29, 1992.A DRAM is capable of regulating an output timing of a read data. The output timing of the read data can be regulated by the DRAM which has a circuit (127) for counting the number of clock pulses until the read data is transferred to a data latch circuit (121) and a circuit (129) for outputting the counted number. The DRAM has a circuit (125) which can regulate the output timing in response to an external input signal.
|
