发明名称 |
Integrated circuit memory with asymmetric row access topology |
摘要 |
A DRAM or VRAM integrated circuit memory of the divided bit line design includes a first bit line pair divided into a first pair of bit line halves and a second pair of bit line halves, and second bit line pair divided into a third pair of bit line halves and a fourth pair of bit line halves. A row decoder addresses a row associated with the first pair of bit line halves during a first time period, addresses a row associated with the second pair of bit line halves in a second time period, addresses a row associated with the third pair of bit line halves in the first time period, and addresses a row associated with the fourth pair of bit line halves in the second time period. The access topology is thus asymmetric with respect to a column decoder connected to the second and third pairs of bit line halves.
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申请公布号 |
US5311478(A) |
申请公布日期 |
1994.05.10 |
申请号 |
US19920931590 |
申请日期 |
1992.08.18 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
ZAGAR, PAUL S.;MCLAURY, LOREN L. |
分类号 |
G11C11/408;G11C11/4097;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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