Integrated circuit memory device having flash clear

摘要

A dual-port memory device provides bit lines having a crossover pattern to reduce stray end coupling capacitances. Such crossover occurs approximately in the middle of the memory array for the device. Data in one-half of the array is stored in an inverted manner from data in the other half of the array. A preferred technique for clearing a memory provides for resetting only a portion of the bits of the array for each entry, with the bits of all memory entries being reset simultaneously. In order to provide such a reset function with the preferred bit line crossover scheme, a voltage node used for reset must also provide signal lines which are crossed over in the middle of the array.