| 摘要 |
The present invention relates to a semiconductor memory cell. The memory cell comprises a word line, a pair of bit lines crossing the word line, a resistance having a first side connected to a high power source and a second side connected to a first connecting node, a first FET connected between the first connecting node and a low power source and having a gate connected to a second connecting node, a second FET connected between the second connecting node and the low power source and having a gate connected to the first connecting node, a third FET connected between the first connecting node and one of the pair of bit lines and having a gate connected to the word line to control the operation of the third FET by changing the potential of the word line, and a fourth FET connected between the second connecting node and the other of the pair of bit lines and having a gate connected to the word line to control the operation of the fourth FET by changing the potential of the word line.
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