| 摘要 |
PURPOSE:To provide a PLL circuit by which an oscillation frequency with fine frequency step interval can be stably obtained and which responds in a sufficiently short time. CONSTITUTION:The frequency division ratio of a frequency division circuit 1 is controlled corresponding to the output of the count value of a frequency division circuit 2 which further frequency-divides the output of the frequency division circuit 1, and a non-uniformalized pulse string in a time series can be obtained. Furthermore, after a compensation signal generated at a compensation signal generation circuit 5 is added on a phase error signal obtained by performing the phase comparison of a reference frequency signal with the pulse string based on the output of the frequency division circuit 2, and a fluctuation component according to non-uniformity in the time series included in the phase error signal is negated, it is outputted to a voltage controlled frequency oscillation circuit 7 as a voltage control signal. |
