发明名称 FIXED POINT MULTIPLYING METHOD
摘要 PURPOSE:To provide the method for enabling multiplication to a fixed point, for which the sum of a bit length at an integral part and a bit length at a decimal part is made much longer, in the case of providing the fixed point multiplying method for a computer by using integral multiplication. CONSTITUTION:In the case of multiplying a multiplier and a multiplicand expressed by integral part L bits and decimal part M bits, a value (11) shifting the multiplier to the least significant side for M bits and a value (12) ignoring the decimal point position of the multiplicand are respectively defined as integers and a first intermediate result (13) multiplying those integers is provided. A value (21) shifting the multiplicand to the least significant side for M bits and a value (22) ignoring the decimal point position at the decimal part of the multiplier are respectively defined as integers, and second intermediate result (23) multiplying those integers is provided. Further, a fourth intermediate result (40) is provided by shifting a third intermediate result (33), for which decimal point positions of a decimal part (31) of the multiplier and a decimal part (32) of the multiplicand are ignored and respectively defined as integers and those integers are multiplied, to the least significant side for M bits. Then, a final multiplied result (51) of the multiplier and the multiplicand is provided by integrally adding the first, second and fourth intermediate results (13, 23 and 40).
申请公布号 JPH06124191(A) 申请公布日期 1994.05.06
申请号 JP19920274079 申请日期 1992.10.13
申请人 MITSUBISHI ELECTRIC CORP 发明人 SAKAMOTO TADASHI;TAKITA HIROKI;SHIMIZU TORU
分类号 G06F7/38;G06F7/52;G06F7/523;G06F7/53 主分类号 G06F7/38
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