| 摘要 |
<p>PURPOSE:To enable performing erasing in which erasing verification time is shortened, a time required to erase can be shortened, while a cell transistor overly erased does not occur. CONSTITUTION:Reference voltage Vref is assumed as 'the lowest limit threshold allowed to VCC-cell transistors 1100-1122'. And word lines WL0-WL2 and a source lines SL are made VCC, nMOS transistors 120-122 and 29 are made an ON state (gate voltage =VCC + Vth - n), erasing verification is performed by comparing a voltage value of a data bus 13 with a voltage value of the reference voltage Vref.</p> |
