发明名称 |
METHOD AND DEVICE FOR CONTROLLING CLOCK SKEW |
摘要 |
<p>PURPOSE: To facilitate time delay adjustments by providing a time delay generating means which guarantees the delay time difference between a primary clock signal and a master clock signal on a master clock output line within a specific time range. CONSTITUTION: The master clock signal distributed to master clock output lines is supplied to a circuit through a line 140. The circuit has serial programmable delay blocks connected to respective clock outputs and for the signal sent to the 1st programmable delay block 138, a fuse circuit 160 selects which of inputs 147 and 149 is sent out from the output 150 of a multiplexer 148 and outputs it. Namely, when a fuse 166 is not disconnected, the multiplexer 148 outputs the clock signal from an inverter 142 after it is delayed by 8 gates. When the fuse 166 is blown by applying a sufficient current to a terminal 162, the multiplexer 148 outputs the undelayed master clock signal.</p> |
申请公布号 |
JPH06124137(A) |
申请公布日期 |
1994.05.06 |
申请号 |
JP19920010412 |
申请日期 |
1992.01.23 |
申请人 |
BITETSUSE SEMICONDUCTOR CORP |
发明人 |
AIRA DEIMII;ROBAATO ENU DEMINGU;UIRIAMU SHII TERERU;DEIBITSUDO DABURIYUU HETSUJIZU |
分类号 |
G06F1/10;H03K5/00;H03K5/13;H03K5/15;(IPC1-7):G06F1/10 |
主分类号 |
G06F1/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|