| 摘要 |
The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.
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| 申请人 |
SIEMENS AG, 80333 MUENCHEN, DE |
发明人 |
ABERT, MICHAEL, DIPL.-ING., 7551 AU, DE;BLOCK, SIEGFRIED, DIPL.-ING., 6744 KANDEL, DE;BOZENHARDT, JOHANNES, DIPL.-ING., 7505 ETTLINGEN, DE;LEIGSNERING, FRANZ, 7505 ETTLINGEN, DE;PFATTEICHER, WERNER, DIPL.-ING. (FH), 7507 PFINZTAL, DE;SCHEWE, FRANZ-CLEMENS, 7500 KARLSRUHE, DE |
