COMMUNICATION PATH BUS SELECTING METHOD

摘要

The processor employing the method improves the reliability of error process and speeds up the process. The method employs a low level main board (1), a low level interface boards (2,8) which comprises GPIP and DDR, a hardware units(12 or 15) which connect low level interface board to TD-bus(6). The method includes a lst step (102) which selects one of hardware units (15 or 17) via a parameter, a 2nd step (104) which reads or writes a registor of GPIR and assigns GPIR to hardware port address (103), a 3rd step which assigns DDR to hardware signal and data input-output direction, and a 4th step which selects a bus through bits 4,7.