| 摘要 |
A single chip video signal processing circuit capable of performing a sync separation and odd/even field detection using an NTSC mode or a PAL mode video signal, the video signal processing circuit includes a sync signal separator for separating the input video signal into a horizontal sync signal and a composite sync signal, a vertical sync signal detector for detecting a vertical sync signal from the composite sync signal, a window pulse generator for generating a window pulse having a different width according to the selection of either the NTSC mode or the PAL mode by combining the detected vertical sync signal with the horizontal sync signal, an odd/even field detector for receiving the window pulse and the vertical sync signal and for detecting the number of pulses of the vertical sync signal within the window pulse interval, and a vertical blanking interval detector for counting a predetermined number of pulses of the horizontal sync signal, the window pulse being used as a RESET pulse for generating a vertical blanking pulse.
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