发明名称 FREQUENCY COUNTER CIRCUIT
摘要 PURPOSE:To simplify the measurement of the mean value of a generation frequency by constituting a circuit so that an increase and decrease in generation frequency of pulses generated at random will be outputted being compressed. CONSTITUTION:Pulse generating circuit 6 outputs out-of-phase clock signals phi1 and phi2 of a constant period. Input pulse signal F1 is also sampled in synchronizing circuit 3 by signal phi1 to obtain pulse signal F11. Similarly, pulse signal F2 generated by pulse generating circuit 2 is sampled in synchronizing circuit 5 by signal phi2 to obtain pulse signal F22. On detecting the continuation of not less than two input signals F11 and F22, detection circuit 4 outputs pulse signals FU and FD one by one. By receiving input signals FU and FD, up-down counter 1 ouputs two-level pulse signal Ct obtained by compressing outputs of ''1'' and ''0''.
申请公布号 JPS5583343(A) 申请公布日期 1980.06.23
申请号 JP19780159470 申请日期 1978.12.20
申请人 MITSUBISHI ELECTRIC CORP 发明人 HASEGAWA MASAKAZU
分类号 G01D1/08;G01D3/02;G01T1/17;H03K21/00;H03K21/02;H03K23/00 主分类号 G01D1/08
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