| 摘要 |
PURPOSE:To reduce test man-hours in a dynamic RAM etc., and to enhance utilizing efficiency in a test device by shortening a time required for a distur bance refreshing test in the dynamic RAM etc., without necessitating disturbance access. CONSTITUTION:Switch MOSFETs Q1-Q8 turned on at the time of the disturbance refreshing test are provided between complementary bit lines BO*-Bn* and substrate voltage VBB. Further, the disturbance refreshing test in the dynamic RAM, etc., is executed by turning on the switch MOSFETs Q1-Q8 simultaneously after test data so that an information storage node becomes a high level is written in all memory cells. Thus, relatively large stress exceeding the absolute value of power source voltage is applied to all memory cells simultaneously without necessitating the disturbance access, and meanwhile, the test device is released. |
